`timescale 1ps/1ps
module tb_ASYNC_FIFO;
reg WCLK;
reg RCLK;
reg RSTN;
reg WINC;
reg RINC;
reg [15:0]WDATA;
wire [15:0]RDATA;

ASYNC_FIFO ASYNC_FIFO_INST
(
    .RSTN   (RSTN),
    .WCLK   (WCLK),
    .RCLK   (RCLK),
    .WINC    (WINC),
    .RINC    (RINC),
    .WDATA   (WDATA),
    .RDATA  (RDATA)
);

localparam WCLK_PERIOD = 34;
localparam RCLK_PERIOD = 22;
always #(WCLK_PERIOD/2) WCLK=~WCLK;
always #(RCLK_PERIOD/2) RCLK=~RCLK;

initial begin
    $dumpfile("tb_ASYNC_FIFO.vcd");
    $dumpvars(0, tb_ASYNC_FIFO);
end

initial begin
    WCLK <= 0; RCLK <= 0;
    WINC <= 0; RINC = 0;
    RSTN <= 0;WDATA = 0;
    #50
    RSTN <= 1;
    #52
    WINC <= 1;
    WDATA <= 16'h1234;
    #34
    WDATA <= 16'h3456;
    #34
    WDATA <= 16'h789a;
    #34
    WDATA <= 16'hbcde;
    #34
    WINC <= 0;
    #100 
    RINC <= 1;
    #1000
    RINC <= 0;
    #10000
    $finish(2);
end

endmodule
